rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Verification methodology manual for system verilog
  name:
    name part: Bergeron, Janick
    role:
      role term: creator
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: nyu
    place:
      place term: New York
    publisher: Springer
    date issued: c 2006
    date issued: 2006
    issuance: monographic
  language:
    language term: gre
  physical description:
    form: print
    extent: xvii. , 503 σ. : εικ. ; 24 εκ.
  note: Bergeron, Janick ... [et al.].
  note: Περιλαμβάνει βιβλιογραφίες και ευρετήριο.
  subject:
    topic: VERILOG (COMPUTER HARDWARE DESCRIPTION LANGUAGE)
  subject:
    topic: INTERGRATED CIRCUITS--VERIFICATION
  classification: 621.392
  identifier: 0387255389
  record info:
    record content source: GrPaTEI
    record creation date: 090313
    record identifier: GR-Antirio659
    language of cataloging:
      language term: gre
    language of cataloging:
      language term: gre
    language of cataloging:
      language term: gre