http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Conference Proceedings of the 10th Annual International Symposium June 13-17, 1983. ACM SIGARCH NEWSLETTER: Vol. 11, No. 3, 1983
Session 1 : Introduction and Keynote Speech Size, Power, and Speed Session 2 : Computer Architecture Taxonomy Towards a Taxonomy of Computer Architecture Based on thw Machine Data Type View Framework for a Taxonomy of Fault - Tolerance Attributes in Computer Systems Session 3 : Architecture Design Methods Caddie - An Interactive Design Environment On the Verification of Computer Architecture Using an Architecture Description Language Research on Synthesis of Concurrent Computing Systems Session 4 : VLSI Architectures Architecture of the PSC : A programmable Systolic Chip Synchronizing Large VLSI Processor Arrays The Boolean Vector Machine A VLSI Area Machine for Relational Data Bases Session 5A : Data Flow Architecture I Implementing Streams on a Data Flow Computer System with Paged Memory The Piecewise Data Flow Architecture Control Flow and Register Management On the Working Set Concept for Data - Flow Machines A Data Driven System Based on a Microprogrammed Processor Module Session 5B : Cache Memories Architecture of a VLSI Instruction Cache for a RISC Performance of Shared Cache for Parallel - Pipelined Computer Systems Using Cache Memory to Reduce Processor - Memory Traffic A Study of Instruction Cache Organizations and Replacement Policies Section 6A : Multiple Functional Unit Processors Very Long Instruction Word Architectures and the ELI -512 A User - Microprogrammable, Local Host Computer with Low-Level Parallelismk Session 6B : Reliability Combining Tags with Error Codes Fault Diagnosis of Bit - Splice Processor Section 7A : Interconnection Networka I Line Digraph Interations and the (d, k) Problem for Directed Graphs Resourcw Allocation in Rectangular CC-Banyans Uniform Theory of the Shuffle-Exchange Type Permutation Networks Section 7B : Performance Evaluation of Scientific Computers Analysis of Gray - 1S Architecture Performance Measurements on HEP - A Pipelined MIMD Computer (SM)2 : Sparse matrix Solving Machine Session 8: Educational Aspects of Computer Architecture An Experimental System for Computer Science Instruction Session 9A : Data Flow Architectures II Execution Control and Memory Science Instruction DDDP : A DIstibuted Data Driven Processor A Data Flow Processor Array System : Design and Anlysis Session 9B : processor and I/O Architectures A Restospective on the Dorado, A High - Performance Personal Computer System / 370 Extended Architecture : A Program View of the Channel Subsystem Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets Session 10A : Interconnection Networks II Switching Strategies in a Class of Packet Switching Networks A Comparative Study of Distributed Resource Sharing on Multiprocessors Concurrent Error Detection in VLSI Interconnection Networks Session 10B : Multicomputers and Multiprocessors Hierarchical Function Distribution - A Design Principle for Advanced Multicomputer Architectures EMMA : An Industrial Experience on Large Multiprocessing Architectures A Communication Structure for a Multiprocessor Computer with Distributed Global Memory Session 11A : Architectural Support for High Level Languages ALPHA : A High - Performance LISP Machine Equipped with a New Stack Structure and Carbage Collection System A Parallel Execution Model of Logic Programs A System Architecture for the Concurrent Evaluation of Applicative Program Expressions A Performance Evaluation of a Lisp - Based Data -Driven Machine (EM3) Session 11B : Architectures for Image Processing A Pyramidal Approach to Parallel Processing The Design of a Parallel Processor for Image Processing On-Board Satellites: An Application Oriented Approach LINKS-1 : A Parallel Pipelined Multimicrocomputer System for Image Creation LIPP - A SIMD Multiprocessor Architecture for Image Processing Special Day : Applied Artificial Intelligence and Its Influence on Computer Architecture The New Generation of Computer Architecture Inference Machine Overview to the Fifth Generation Computer System Project A Relational Data Base Machine : First Step to Knowledge Base Machine A Critique of Multiprocessing von Neumann Style Author Index
Includes bibliography, Author Index pp. 437-438