rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Principles of Verifiable RTL Design
    sub title: A Functional Coding Style Supporting Verification Processes in Verilog
  name:
    name part: Bening, Lionel.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Foster, Harry.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2000
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XVII, 253 p. 19 illus. online resource.
  abstract: Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process. The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.
  table of contents: The Verification Process -- RTL Methodology Basics -- RTL Logic Simulation -- RTL Formal Verification -- Verifiable RTL Style -- The Bad Stuff -- Verifiable RTL Tutorial -- Principles of Verifiable RTL Design.
  note: by Lionel Bening, Harry Foster.
  subject:
    topic: Engineering
  subject:
    topic: Computer hardware
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Electrical engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Computer Hardware
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  subject:
    topic: Electrical Engineering
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9780306470165
  identifier: http://dx.doi.org/10.1007/b116517
  record info:
    record creation date: 100301
    record change date: 20151204180439.0
    record identifier: 978-0-306-47016-5