rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Logic Synthesis and Verification Algorithms
  name:
    name part: Hachtel, Gary D.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Somenzi, Fabio.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 1996
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XXXII, 564 p. online resource.
  abstract: Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
  table of contents: A Quick Tour of Logic Synthesis with the Help of a Simple Example -- Two Level Logic Synthesis -- Boolean Algebras -- Synthesis of Two-Level Circuits -- Heuristic Minimization of Two-level Circuits -- Binary Decision Diagrams (BDDs) -- Models of Sequential Systems -- Models of Sequential Systems -- Synthesis and Verification of Finite State Machines -- Finite Automata -- Multilevel Logic Synthesis -- Multi-Level Logic Synthesis -- Multi-Level Minimization -- Automatic Test Generation for Combinational Circuits -- Technology Mapping.
  note: by Gary D. Hachtel, Fabio Somenzi.
  subject:
    topic: Engineering
  subject:
    topic: Computer logic
  subject:
    topic: Computer science
    topic: Mathematics
  subject:
    topic: Computers
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Electrical engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Logics and Meanings of Programs
  subject:
    topic: Electrical Engineering
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  subject:
    topic: Discrete Mathematics in Computer Science
  subject:
    topic: Computing Methodologies
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9780306475924
  identifier: http://dx.doi.org/10.1007/b117060
  record info:
    record creation date: 100301
    record change date: 20151204155237.0
    record identifier: 978-0-306-47592-4