rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Systematic Design for Optimisation of Popelined ADCs
  name:
    name part: Goes, João.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Vital, João C.
    role:
      role term: author.
  name:
    name part: Franca, José.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2001
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XV, 160 p. online resource.
  abstract: Systematic Design for Optimisation of Pipelined ADCs proposes and develops new strategies, methodologies and tools for designing low-power and low-area CMOS pipelined A/D converters. The task is tackled by following a scientifically-consistent approach. First of all, the state of the art in pipeline A/D converters is analysed with a double purpose: a) to identify the best suited among different strategies reported in literature and taking into account the objectives pursued; b) to identify the drawbacks of these strategies as a basic first step to improve them. Then, the book proposes a top-down design approach for implementing high-performance low-power and low-area CMOS pipelined A/D converters through: The conception, development and implementation of self-calibrated techniques to extend the linearity of some critical stages in the architecture of pipelined ADCs. The detailed analysis and modelling of some major non-idealities that limit the physical realisation of pipelined ADCs and the proposal, development and implementation of design methodologies to support systematic design of optimised instances of these converters which combine maximum performance with minimum power dissipation and minimum area occupation. £/LIST£ Several implementations together with consistent measured results are presented. In particular, a practical realisation of a low-power 14-bit 5MS/s CMOS pipelined ADC with background analogue self-calibration is fully described. The proposed approach is fully in line with the best practice regarding the design of mixed-signal integrated circuits. On the one hand, drawbacks of currently existing solutions are overcame through innovative strategies and, on the other hand, the expert knowledge is packaged and made available for re-usability by the community of circuit designers. Finally, feasibility of the strategies and the associated encapsulated knowledge is granted through experimental validation of working silicon. Systematic Design for Optimi…
  table of contents: General Design Considerations in Pipelined A/D Converters -- Analogue Code-by-code Self-calibration Technique -- Systematic Design Methodology for Optimisation of High-speed Self-calibrated Pipelined ADCs -- Design of a 14-Bit 5 MS/S CMOS Pipelined A/D Converter -- Integrated Prototypes of Pipelined ADCs and Measured Results -- Conclusions.
  note: by João Goes, João C. Vital, José Franca.
  subject:
    topic: Engineering
  subject:
    topic: Electrical engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Electrical Engineering
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  related item:
    title info:
      title: The International Series in Engineering and Computer Science, 607
  identifier: 9780306481932
  identifier: http://dx.doi.org/10.1007/b100749
  record info:
    record creation date: 100301
    record change date: 20151204145945.0
    record identifier: 978-0-306-48193-2