rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Verification by Error Modeling
    sub title: Using Testing Techniques in Hardware Verification
  name:
    name part: Radecka, Katarzyna.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Zilic, Zeljko.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2003
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XV, 216 p. online resource.
  abstract: 1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be “imminently doable” by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.
  table of contents: Boolean Function Representations -- Don’t Cares and Their Calculation -- Testing -- Design Error Models -- Design Verification by At -- Identifying Redundant Gate and Wire Replacements -- Conclusions and Future Work.
  note: by Katarzyna Radecka, Zeljko Zilic.
  subject:
    topic: Engineering
  subject:
    topic: Computers
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Robotics
  subject:
    topic: Automation
  subject:
    topic: Electrical engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Robotics and Automation
  subject:
    topic: Circuits and Systems
  subject:
    topic: Electrical Engineering
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  subject:
    topic: Computing Methodologies
  classification: TJ210.2-211.495
  classification: T59.5
  classification: 629.892
  related item:
    title info:
      title: Springer eBooks
  related item:
    title info:
      title: Frontiers in Electronic Testing, 25
  identifier: 9780306487392
  identifier: http://dx.doi.org/10.1007/b105974
  record info:
    record creation date: 100301
    record change date: 20151204171416.0
    record identifier: 978-0-306-48739-2