rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Scalable Hardware Verification with Symbolic Simulation
  name:
    name part: Bertacco, Valeria.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2006
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XX, 180 p. 40 illus. online resource.
  abstract: Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions. In structuring this book, the author’s hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research. Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field.
  table of contents: Design and Verification of Digital Systems -- Symbolic Simulation -- Compacting Intermediate States -- Approximate Simulation -- Exact Parametrizations -- Conclusion.
  note: by Valeria Bertacco.
  subject:
    topic: Engineering
  subject:
    topic: Computer hardware
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Electrical engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  subject:
    topic: Computer Hardware
  subject:
    topic: Electrical Engineering
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9780387299068
  identifier: http://dx.doi.org/10.1007/0-387-29906-8
  record info:
    record creation date: 100301
    record change date: 20151204185514.0
    record identifier: 978-0-387-29906-8