rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Writing Testbenches using System Verilog
  name:
    name part: Bergeron, Janick.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2006
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XXVI, 412 p. online resource.
  abstract: Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all. Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model. Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog.
  table of contents: What is Verification? -- Verification Technologies -- The Verification Plan -- High-Level Modeling -- Stimulus and Response -- Architecting Testbenches -- Simulation Management.
  note: by Janick Bergeron.
  subject:
    topic: Engineering
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Quality control
  subject:
    topic: Reliability
  subject:
    topic: Industrial safety
  subject:
    topic: Electrical engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  subject:
    topic: Electrical Engineering
  subject:
    topic: Quality Control, Reliability, Safety and Risk
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9780387312750
  identifier: http://dx.doi.org/10.1007/0-387-31275-7
  record info:
    record creation date: 100301
    record change date: 20151204162249.0
    record identifier: 978-0-387-31275-0