http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Standardized Functional Verification describes the science of functional verification that applies to any digital hardware system. With a precise and comprehensive terminology this book describes a thorough technical framework for achieving superior results with greater efficiency. It also defines a scientific basis for achieving functional closure and shows how true functional closure can be measured by software. The author provides a wealth of practical guidance to the practicing professional. It describes how to compare results from differing projects and how to assess the risk of functional bugs at tape-out or at any other critical product juncture. The book also shows consumers how to compare IP offerings from multiple vendors. For producers, it describes how to verify IP in a manner that meets customer needs. Producers and consumers of silicon IP therefore have a solid framework to communicate requirements and to align expectations effectively and efficiently. Standardized Functional Verification is a valuable reference for verification engineers and managers, and also for developers of verification software. The principles and theory this book describes will drive creation of the next generation of verification tools.
A Brief Overview of Functional Verification -- Analytical Foundation -- Exploring Functional Space -- Planning and Execution -- Normalizing Data -- Analyzing Results -- Assessing Risk.
Computer-Aided Engineering (CAD, CAE) and Design
Electronics and Microelectronics, Instrumentation