http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia
International Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of referred international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit www.springer.com. For more information about IFIP, please visit www.ifip.org.
Molecular Electronics – Devices and Circuits Technology -- Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals -- A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures -- Defragmentation Algorithms for Partially Reconfigurable Hardware -- Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits -- 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System -- Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms -- A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis -- Issues in Model Reduction of Power Grids -- A Traffic Injection Methodology with Support for System-Level Synchronization -- Pareto Points in SRAM Design Using the Sleepy Stack Approach -- Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs -- Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping -- A Novel MicroPhotonic Structure for Optical Header Recognition -- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint -- On-chip Pseudorandom Testing for Linear and Nonlinear MEMS -- Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles -- On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction -- Exact BDD Minimization for Path-Related Objective Functions -- Current Mask Generation: an Analog Circuit to Thwart DPA Attacks -- A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.
edited by Ricardo Reis, Adam Osseiran, Hans-Joerg Pfleiderer.
IFIP International Federation for Information Proc, 240