rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Wafer Level 3-D ICs Process Technology
  name:
    name part: Tan, Chuan Seng.
    role:
      role term: editor.
  name:
    name part: Gutmann, Ronald J.
    role:
      role term: editor.
  name:
    name part: Reif, L. Rafael.
    role:
      role term: editor.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2008
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XII, 410 p. online resource.
  abstract: Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration. Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration.
  table of contents: Overview of Wafer-Level 3D ICs -- Monolithic 3D Integrated Circuits -- Stacked CMOS Technologies -- Wafer-Bonding Technologies and Strategies for 3D ICs -- Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies -- Cu Wafer Bonding for 3D IC Applications -- Cu/Sn Solid#x2013;Liquid Interdiffusion Bonding -- An SOI-Based 3D Circuit Integration Technology -- 3D Fabrication Options for High-Performance CMOS Technology -- 3D Integration Based upon Dielectric Adhesive Bonding -- Direct Hybrid Bonding -- 3D Memory -- Circuit Architectures for 3D Integration -- Thermal Challenges of 3D ICs -- Status and Outlook.
  note: edited by Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif.
  subject:
    topic: Engineering
  subject:
    topic: Electronics
  subject:
    topic: Microelectronics
  subject:
    topic: Optical materials
  subject:
    topic: Electronic materials
  subject:
    topic: Materials
    topic: Surfaces
  subject:
    topic: Thin films
  subject:
    topic: Engineering
  subject:
    topic: Electronics and Microelectronics, Instrumentation
  subject:
    topic: Optical and Electronic Materials
  subject:
    topic: Surfaces and Interfaces, Thin Films
  subject:
    topic: Engineering, general
  classification: TK7800-8360
  classification: TK7874-7874.9
  classification: 621.381
  related item:
    title info:
      title: Springer eBooks
  related item:
    title info:
      title: Integrated Circuits and Systems
  identifier: 9780387765341
  identifier: http://dx.doi.org/10.1007/978-0-387-76534-1
  record info:
    record creation date: 100301
    record change date: 20151204172317.0
    record identifier: 978-0-387-76534-1