rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Design for Manufacturability and Yield for Nano-Scale CMOS
  name:
    name part: Chiang, Charles C.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Kawa, Jamil.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: ne
    date issued: 2007
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XXVII, 255 p. online resource.
  abstract: As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect ratio metallurgies. This reality has resulted in three main manufacturability issues that have to be addressed: printability, planarization, and intra-die variability. Addressing in depth the fundamentals impacting those three issues at all the stages of the design process is not a luxury one can ignore. Manufacturability and yield are now one and the same and are no longer a fabrication, packaging, and test concerns; they are the concern of the whole IC community. Yield and manufacturability have to be designed in, and they are everybody’s responsibility. Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design’s manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.
  table of contents: Random Defects -- Systematic Yield - Lithography -- Systematic Yield - Chemical Mechanical Polishing (CMP) -- Variability & Parametric Yield -- Design for Yield -- Yield Prediction -- Conclusions.
  note: by Charles C. Chiang, Jamil Kawa.
  subject:
    topic: Engineering
  subject:
    topic: Microprocessors
  subject:
    topic: Software engineering
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Electronics
  subject:
    topic: Microelectronics
  subject:
    topic: Electronic circuits
  subject:
    topic: Nanotechnology
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Electronics and Microelectronics, Instrumentation
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  subject:
    topic: Processor Architectures
  subject:
    topic: Software Engineering/Programming and Operating Systems
  subject:
    topic: Nanotechnology
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  related item:
    title info:
      title: Series on Integrated Circuits and Systems
  identifier: 9781402051883
  identifier: http://dx.doi.org/10.1007/978-1-4020-5188-3
  record info:
    record creation date: 100301
    record change date: 20151204152953.0
    record identifier: 978-1-4020-5188-3