http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Interconnect-Centric Design for Advanced SoC and NoC
In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.
Physical and Electrical Issues -- System-on-Chip-Challenges in the Deep-Sub-Micron Era -- Wires as Interconnects -- Global Interconnect Analysis -- Design Methodologies for on-Chip Inductive Interconnect -- Clock Distribution for High Performance Designs -- Logical and Architectural Issues -- Error-Tolerant Interconnect Schemes -- Power Reduction Coding for Buses -- Bus Structures in Network-on-Chips -- From Buses to Networks -- Arbitration and Routing Schemes for on-Chip Packet Networks -- Design Methodology and Tools -- Self-Timed Approach for Noise Reduction in NoC Reduction in NoC -- Formal Communication Modeling and Refinement -- Network-Centric System-Level Model for Multiprocessor Soc Simulation -- Socket-Based Design Using Decoupled Interconnects -- Application Cases -- Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV -- A Brunch from the Coffee Table-Case Study in NoC Platform Design.
edited by Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, Axel Jantsch.
Software Engineering/Programming and Operating Systems
Computer-Aided Engineering (CAD, CAE) and Design