rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Timing
  name:
    name part: Sapatnekar, Sachin.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2004
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XII, 294 p. online resource.
  abstract: Statistical timing analysis is an area of growing importance in nanometer te- nologies‚ as the uncertainties associated with process and environmental var- tions increase‚ and this chapter has captured some of the major efforts in this area. This remains a very active field of research‚ and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits‚ a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book‚ the reader is referred to [LNPS00‚ HN01‚ JH01‚ ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs.
  table of contents: Preduction/Introface -- A Quick Overview of Circuit Simulation -- Frequency-Domain Analysis of Linear Systems -- Timing Analysis for a Combinational Stage -- Timing Analysis for Combinational Circuits -- Statistical Static Timing Analysis -- Timing Analysis for Sequential Circuits -- Transistor-Level Combinational Timing Optimization -- Clocking and Clock Skew Optimization -- Retiming -- Conclusion.
  note: by Sachin Sapatnekar.
  subject:
    topic: Engineering
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Electrical engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Electrical Engineering
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9781402080227
  identifier: http://dx.doi.org/10.1007/b117318
  record info:
    record creation date: 100301
    record change date: 20151204162943.0
    record identifier: 978-1-4020-8022-7