rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Functional Design Errors in Digital Circuits
    sub title: Diagnosis, Correction and Repair
  name:
    name part: Chang, Kai-hui.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Markov, Igor L.
    role:
      role term: author.
  name:
    name part: Bertacco, Valeria.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: ne
    date issued: 2009
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XXIV, 200 p. online resource.
  abstract: Due to the dramatic increase in design complexity, modern circuits are often produced with functional errors. While improvements in verification allow engineers to find more errors, fixing these errors remains a manual and challenging task. Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. In particular, this book describes: (1) techniques for bug trace minimization that simplify debugging; (2) an RTL error diagnosis method that identifies the root cause of errors directly; (3) a counterexample-guided error-repair framework to automatically fix errors in gate-level and RTL designs; (4) a symmetry-based rewiring technology for fixing electrical errors; (5) an incremental verification system for physical synthesis; and (6) an integrated framework for post-silicon debugging and layout repair. In addition, Functional Design Errors in Digital Circuits Diagnosis describes a comprehensive evaluation of spare-cell insertion methods. The solutions provided in this book can greatly reduce debugging effort, enhance design quality, and ultimately enable the design and manufacture of more reliable electronic devices.
  table of contents: Background and Prior Art -- Current Landscape in Design and Verification -- Finding Bugs and Repairing Circuits -- FogClear Methodologies and Theoretical Advances in Error Repair -- Circuit Design and Verification Methodologies -- Counterexample-Guided Error-Repair Framework -- Signature-Based Resynthesis Techniques -- Symmetry-Based Rewiring -- FogClear Components -- Bug Trace Minimization -- Functional Error Diagnosis and Correction -- Incremental Verification for Physical Synthesis -- Post-Silicon Debugging and Layout Repair -- Methodologies for Spare-Cell Insertion -- Conclusions.
  note: by Kai-hui Chang, Igor L. Markov, Valeria Bertacco.
  subject:
    topic: Engineering
  subject:
    topic: Logic design
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  subject:
    topic: Logic Design
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  related item:
    title info:
      title: Lecture Notes in Electrical Engineering, 32
  identifier: 9781402093654
  identifier: http://dx.doi.org/10.1007/978-1-4020-9365-4
  record info:
    record creation date: 100301
    record change date: 20151121052056.0
    record identifier: 978-1-4020-9365-4