rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: On and Off-Chip Crosstalk Avoidance in VLSI Design
  name:
    name part: Duan, Chunjie.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: LaMeres, Brock J.
    role:
      role term: author.
  name:
    name part: Khatri, Sunil P.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2010
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XXIV, 240 p. online resource.
  abstract: On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.
  table of contents: On-Chip Crosstalk and Avoidance -- of On-Chip Crosstalk Avoidance -- Preliminaries to On-chip Crosstalk -- Memoryless Crosstalk Avoidance Codes -- CODEC Designs for Memoryless Crosstalk Avoidance Codes -- Memory-based Crosstalk Avoidance Codes -- Multi-valued Logic Crosstalk Avoidance Codes -- Summary of On-Chip Crosstalk Avoidance -- Off-Chip Crosstalk and Avoidance -- to Off-Chip Crosstalk -- Package Construction and Electrical Modeling -- Preliminaries and Terminology -- Analytical Model for Off-Chip Bus Performance -- Optimal Bus Sizing -- Bus Expansion Encoder -- Bus Stuttering Encoder -- Impedance Compensation -- Future Trends and Applications -- Summary of Off-Chip Crosstalk Avoidance.
  note: by Chunjie Duan, Brock J. LaMeres, Sunil P. Khatri.
  subject:
    topic: Engineering
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9781441909473
  identifier: http://dx.doi.org/10.1007/978-1-4419-0947-3
  record info:
    record creation date: 100301
    record change date: 20151125231402.0
    record identifier: 978-1-4419-0947-3