rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
  name:
    name part: Lim, Sung Kyu.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2013
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XXVIII, 560 p. online resource.
  abstract: This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs. Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process. Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability. Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the electro-migration failure mechanisms in TSVs. Covers design-for-thermal-reliability in 3D ICs, including thermal-aware architectural floorplanning, gate-level placement techniques to alleviate thermal problems, and co-design and co-analysis of thermal, power delivery, and performance. Includes issues affecting design-for-mechanical-reliability in 3D ICs, such as the co-efficient of thermal expansion (CTE) mismatch between TSV and silicon substrate, device mobility and full-chip timing variations, and the impact of package elements.
  table of contents: Regular vs Irregular TSV Placementfor 3D IC -- Steiner Routingfor 3D IC -- Buffer Insertion for 3D IC.- Low Power Clock Routing for 3D IC -- Power Delivery Network Design for 3D IC -- 3D Clock Routing for Pre-bond Testability -- TSV-to-TSV Coupling Analysis and Optimization -- TSV Current Crowding and Power Integrity -- Modeling of Atomic Concentration at the Wire-to-TSV Interface -- Multi-Objective Archetectural Floorplanning for 3D IC -- Thermal-aware Gate-level Placement for 3D IC -- 3D IC Cooling with Micro-Fluidic Channels -- Mechanical Reliability Analysis and Optimization for 3D IC -- Impact of Mechanical Stress on Timing Variation for 3D IC -- Chip/Package Co-Analysis of Mechanical Stress for 3D IC -- 3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations -- TSV Interfracial Crack Analysis and Optimization -- Ultra High Logic Designs Using Monolithic 3D Integration -- Impact of TSV Scaling on 3D IC Design Quality -- 3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.
  note: by Sung Kyu Lim.
  subject:
    topic: Engineering
  subject:
    topic: Microprocessors
  subject:
    topic: Nanotechnology
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Nanotechnology and Microengineering
  subject:
    topic: Processor Architectures
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9781441995421
  identifier: http://dx.doi.org/10.1007/978-1-4419-9542-1
  record info:
    record creation date: 121204
    record change date: 20151204171734.0
    record identifier: 978-1-4419-9542-1