rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Heterogeneous Multicore Processor Technologies for Embedded Systems
  name:
    name part: Uchiyama, Kunio.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Arakawa, Fumio.
    role:
      role term: author.
  name:
    name part: Kasahara, Hironori.
    role:
      role term: author.
  name:
    name part: Nojiri, Tohru.
    role:
      role term: author.
  name:
    name part: Noda, Hideyuki.
    role:
      role term: author.
  name:
    name part: Tawara, Yasuhiro.
    role:
      role term: author.
  name:
    name part: Idehara, Akio.
    role:
      role term: author.
  name:
    name part: Iwata, Kenichi.
    role:
      role term: author.
  name:
    name part: Shikano, Hiroaki.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2012
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XII, 224 p. online resource.
  abstract: To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.
  table of contents: Background -- Heterogeneous Multicore Architecture -- Processor Cores -- Chip Implementations -- Software Environments -- Application Programs and Systems.
  note: by Kunio Uchiyama, Fumio Arakawa, Hironori Kasahara, Tohru Nojiri, Hideyuki Noda, Yasuhiro Tawara, Akio Idehara, Kenichi Iwata, Hiroaki Shikano.
  subject:
    topic: Engineering
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9781461402848
  identifier: http://dx.doi.org/10.1007/978-1-4614-0284-8
  record info:
    record creation date: 120420
    record change date: 20151204181427.0
    record identifier: 978-1-4614-0284-8