rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Constraining Designs for Synthesis and Timing Analysis
    sub title: A Practical Guide to Synopsys Design Constraints (SDC)
  name:
    name part: Gangadharan, Sridhar.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Churiwala, Sanjay.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxu
    date issued: 2013
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XXVII, 226 p. online resource.
  abstract: This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. · Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints; · Includes key topics of interest to a synthesis, static timing analysis or place and route engineer; · Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing; · Explains fundamental concepts and provides exact command syntax.
  table of contents: Introduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC.
  note: by Sridhar Gangadharan, Sanjay Churiwala.
  subject:
    topic: Engineering
  subject:
    topic: Microprocessors
  subject:
    topic: Electronics
  subject:
    topic: Microelectronics
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Electronics and Microelectronics, Instrumentation
  subject:
    topic: Processor Architectures
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9781461432692
  identifier: http://dx.doi.org/10.1007/978-1-4614-3269-2
  record info:
    record creation date: 130507
    record change date: 20151105121016.0
    record identifier: 978-1-4614-3269-2