rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: System-level Test and Validation of Hardware/Software Systems
  name:
    name part: Sonza Reorda, Matteo.
    role:
      role term: editor.
  name:
    name part: Peng, Zebo.
    role:
      role term: editor.
  name:
    name part: Violante, Massimo.
    role:
      role term: editor.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: xxk
    date issued: 2005
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XII, 179 p. online resource.
  abstract: New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue. System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: • modeling of bugs and defects; • stimulus generation for validation and test purposes (including timing errors; • design for testability. For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.
  table of contents: Modeling Permanent Faults -- Test Generation: A Symbolic Approach -- Test Generation: A Heuristic Approach -- Test Generation: A Hierarchical Approach -- Test Program Generation from High-level Microprocessor Descriptions -- Tackling Concurrency and Timing Problems -- An Approach to System-level Design for Test -- System-level Dependability Analysis.
  note: edited by Matteo Sonza Reorda, Zebo Peng, Massimo Violante.
  subject:
    topic: Engineering
  subject:
    topic: Computer hardware
  subject:
    topic: Computer programming
  subject:
    topic: Condensed matter
  subject:
    topic: Engineering design
  subject:
    topic: Electronics
  subject:
    topic: Microelectronics
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Electronics and Microelectronics, Instrumentation
  subject:
    topic: Engineering Design
  subject:
    topic: Computer Hardware
  subject:
    topic: Programming Techniques
  subject:
    topic: Condensed Matter Physics
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  related item:
    title info:
      title: Springer Series in Advanced Microelectronics, 17
  identifier: 9781846281457
  identifier: http://dx.doi.org/10.1007/1-84628-145-8
  record info:
    record creation date: 100301
    record change date: 20151204153407.0
    record identifier: 978-1-84628-145-7