rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Long-Term Reliability of Nanometer VLSI Systems
    sub title: Modeling, Analysis and Optimization
  name:
    name part: Tan, Sheldon.
    role:
      role term: creator
    role:
      role term: author.
    role:
      role term: aut
    role:
      role term: http://id.loc.gov/vocabulary/relators/aut
  name:
    name part: Tahoori, Mehdi.
    role:
      role term: author.
    role:
      role term: aut
    role:
      role term: http://id.loc.gov/vocabulary/relators/aut
  name:
    name part: Kim, Taeyoung.
    role:
      role term: author.
    role:
      role term: aut
    role:
      role term: http://id.loc.gov/vocabulary/relators/aut
  name:
    name part: Wang, Shengcheng.
    role:
      role term: author.
    role:
      role term: aut
    role:
      role term: http://id.loc.gov/vocabulary/relators/aut
  name:
    name part: Sun, Zeyu.
    role:
      role term: author.
    role:
      role term: aut
    role:
      role term: http://id.loc.gov/vocabulary/relators/aut
  name:
    name part: Kiamehr, Saman.
    role:
      role term: author.
    role:
      role term: aut
    role:
      role term: http://id.loc.gov/vocabulary/relators/aut
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: gw
    date issued: 2019
    edition: 1st ed. 2019.
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XLI, 460 p. 211 illus., 195 illus. in color. online resource.
  abstract: This book provides readers with a detailed reference regarding two of the most important long-term reliability and aging effects on nanometer integrated systems, electromigrations (EM) for interconnect and biased temperature instability (BTI) for CMOS devices. The authors discuss in detail recent developments in the modeling, analysis and optimization of the reliability effects from EM and BTI induced failures at the circuit, architecture and system levels of abstraction. Readers will benefit from a focus on topics such as recently developed, physics-based EM modeling, EM modeling for multi-segment wires, new EM-aware power grid analysis, and system level EM-induced reliability optimization and management techniques. Reviews classic Electromigration (EM) models, as well as existing EM failure models and discusses the limitations of those models; Introduces a dynamic EM model to address transient stress evolution, in which wires are stressed under time-varying current flows, and the EM recovery effects. Also includes new, parameterized equivalent DC current based EM models to address the recovery and transient effects; Presents a cross-layer approach to transistor aging modeling, analysis and mitigation, spanning multiple abstraction levels; Equips readers for EM-induced dynamic reliability management and energy or lifetime optimization techniques, for many-core dark silicon microprocessors, embedded systems, lower power many-core processors and datacenters.
  table of contents: Part I. New physics-based EM analysis and system-level dynamic reliability management -- Chapter 1. Introduction -- Chapter 2. Physics Based EM Modeling -- Chapter 3. Fast EM Stress Evolution Analysis Using Krylov Subspace Method -- Chapter 4. Fast EM Immortatlity Analysis For Multisegment Copper Interconnect Wires -- Chapter 5. Dynamic EM Models For Transient Stress Evolution and Recovery -- Chapter 6. Compact EM Models for Multi-SEgment Interconnect Wires -- Chapter 7. EM Assesment for Power Grid Networks -- Chapter 8. Resource Based EM Modeling for Multi-Crore Microprocessors -- Chapter 9. DRM and Optimization for Real Time Embedded Systems -- Chapter 10. Learning Based DRM and Energy Optimization for Many Core Dark Silicaon Processors -- Chapter 11. Recovery Aware DRM for Near Threshold Dark Silicon Processors -- Chapter 12. Cross-Layer DRM and Optimization For Datacenter Systems -- Part II. Transistor Aging Effects and Reliability -- 13. Introduction -- Chapter 14. Aging AWare Timings Analysis -- Chapter 15. Aging Aware Standard Cell Library Optimization Methods -- Chapter 16. Aging Effects In Sequential Elements -- Chapter 17. Aging Guardband Reduction Through Selective Flip Flop Optimization -- Chapter 18. Workload Aware Static Aging Monitoring and Mitigation of Timing Critical Flip Flops -- Chapter 19. Aging Relaxation at Micro Architecture Level Using Special NOPS -- Chapter 20. Extratime Modelling and Analyis of Transistor Agin at Microarchitecture Level -- Chapter 21. Reducing Processor Wearout By Exploiting The Timing Slack of Instructions.
  note: by Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr.
  subject:
    topic: Electronic circuits
  subject:
    topic: Microprocessors
  subject:
    topic: Electronic Circuits and Devices
  subject:
    topic: Circuits and Systems
  subject:
    topic: Processor Architectures
  classification: TK7867-7867.5
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9783030261726
  identifier: https://doi.org/10.1007/978-3-030-26172-6
  record info:
    record creation date: 190912
    record change date: 20191029001150.0
    record identifier: 978-3-030-26172-6