rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Flip-Flop Design in Nanometer CMOS
    sub title: From High Speed to Low Energy
  name:
    name part: Alioto, Massimo.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Consoli, Elio.
    role:
      role term: author.
  name:
    name part: Palumbo, Gaetano.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: gw
    date issued: 2015
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XV, 260 p. 123 illus., 5 illus. in color. online resource.
  abstract: This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate and postgraduate students (already familiar with digital circuits and timing). • Provides a unified treatment of Flip-Flop design and energy/variation-aware selection in nanometer CMOS VLSI systems • Offers in-depth analysis of the impact of nanometer effects on design tradeoffs • Presents a comprehensive analysis, by considering more than 20 topologies covering all relevant classes of circuits • Uses a rigorous framework based on novel methodologies to include layout parasitics within the circuit design loop .
  table of contents: The Logical Effort Method -- Design in the Energy-Delay Space -- Clocked Storage Elements -- Flip-Flop Optimized Design -- Analysis and Comparison in the Energy-Delay-Area Domain -- Energy Efficiency Versus Clock Slope -- Hold Time Issues and Impact of variations on Flip-Flop Topologies -- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies.
  note: by Massimo Alioto, Elio Consoli, Gaetano Palumbo.
  subject:
    topic: Engineering
  subject:
    topic: Microprocessors
  subject:
    topic: Electronic circuits
  subject:
    topic: Nanotechnology
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Electronic Circuits and Devices
  subject:
    topic: Processor Architectures
  subject:
    topic: Nanotechnology and Microengineering
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9783319019970
  identifier: http://dx.doi.org/10.1007/978-3-319-01997-0
  record info:
    record creation date: 141014
    record change date: 20151204183450.0
    record identifier: 978-3-319-01997-0