rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Testing of Interposer-Based 2.5D Integrated Circuits
  name:
    name part: Wang, Ran.
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Chakrabarty, Krishnendu.
    role:
      role term: author.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: gw
    date issued: 2017
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XIV, 182 p. 118 illus., 102 illus. in color. online resource.
  abstract: This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.
  table of contents: Introduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.-.
  note: by Ran Wang, Krishnendu Chakrabarty.
  subject:
    topic: Engineering
  subject:
    topic: Logic design
  subject:
    topic: Microprocessors
  subject:
    topic: Electronic circuits
  subject:
    topic: Engineering
  subject:
    topic: Circuits and Systems
  subject:
    topic: Processor Architectures
  subject:
    topic: Logic Design
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9783319547145
  identifier: http://dx.doi.org/10.1007/978-3-319-54714-5
  record info:
    record creation date: 170320
    record change date: 20170320133608.0
    record identifier: 978-3-319-54714-5