rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Low-Power Design and Power-Aware Verification
  name:
    name part: Khondkar, Progyna.
    role:
      role term: creator
    role:
      role term: author.
    role:
      role term: aut
    role:
      role term: http://id.loc.gov/vocabulary/relators/aut
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: gw
    date issued: 2018
    edition: 1st ed. 2018.
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XV, 155 p. 19 illus., 12 illus. in color. online resource.
  abstract: Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers. .
  table of contents: 1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References. .
  note: by Progyna Khondkar.
  subject:
    topic: Electronic circuits
  subject:
    topic: Software engineering
  subject:
    topic: Microprocessors
  subject:
    topic: Computer software-Reusability
  subject:
    topic: Circuits and Systems
  subject:
    topic: Software Engineering
  subject:
    topic: Processor Architectures
  subject:
    topic: Performance and Reliability
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer eBooks
  identifier: 9783319666198
  identifier: https://doi.org/10.1007/978-3-319-66619-8
  record info:
    record creation date: 171005
    record change date: 20191028201936.0
    record identifier: 978-3-319-66619-8