rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Computer Aided Verification
    sub title: 18th International Conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006. Proceedings
  name:
    name part: Ball, Thomas.
    role:
      role term: editor.
  name:
    name part: Jones, Robert B.
    role:
      role term: editor.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: gw
    date issued: 2006
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XV, 564 p. online resource.
  table of contents: Invited Talks -- Formal Specifications on Industrial-Strength Code—From Myth to Reality -- I Think I Voted: E-Voting vs. Democracy -- Playing with Verification, Planning and Aspects: Unusual Methods for Running Scenario-Based Programs -- The Ideal of Verified Software -- Session 1. Automata -- Antichains: A New Algorithm for Checking Universality of Finite Automata -- Safraless Compositional Synthesis -- Minimizing Generalized Büchi Automata -- Session 2. Tools Papers -- Ticc: A Tool for Interface Compatibility and Composition -- FAST Extended Release -- Session 3. Arithmetic -- Don’t Care Words with an Application to the Automata-Based Approach for Real Addition -- A Fast Linear-Arithmetic Solver for DPLL(T) -- Session 4. SAT and Bounded Model Checking -- Bounded Model Checking for Weak Alternating Büchi Automata -- Deriving Small Unsatisfiable Cores with Dominators -- Session 5. Abstraction/Refinement -- Lazy Abstraction with Interpolants -- Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop -- Counterexamples with Loops for Predicate Abstraction -- Session 6. Tools Papers -- cascade: C Assertion Checker and Deductive Engine -- Yasm: A Software Model-Checker for Verification and Refutation -- Session 7. Symbolic Trajectory Evaluation -- SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation -- Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation -- Session 8. Property Specification and Verification -- Some Complexity Results for SystemVerilog Assertions -- Check It Out: On the Efficient Formal Verification of Live Sequence Charts -- Session 9. Time -- Symmetry Reduction for Probabilistic Model Checking -- Communicating Timed Automata: The More Synchronous, the More Difficult to Verify -- Allen Linear (Interval) Temporal Logic – Translation to LTL and Monitor Synthesis -- Session 10. Tools Papers -- DiVinE – A Tool for Distributed Verification -- EverLost: A Flexible Platform…
  note: edited by Thomas Ball, Robert B. Jones.
  subject:
    topic: Computer science
  subject:
    topic: Logic design
  subject:
    topic: Software engineering
  subject:
    topic: Computers
  subject:
    topic: Computer logic
  subject:
    topic: Mathematical logic
  subject:
    topic: Artificial intelligence
  subject:
    topic: Computer Science
  subject:
    topic: Theory of Computation
  subject:
    topic: Logics and Meanings of Programs
  subject:
    topic: Software Engineering
  subject:
    topic: Mathematical Logic and Formal Languages
  subject:
    topic: Artificial Intelligence (incl. Robotics)
  subject:
    topic: Logic Design
  classification: QA75.5-76.95
  classification: 004.0151
  related item:
    title info:
      title: Springer eBooks
  related item:
    title info:
      title: Lecture Notes in Computer Science, 4144
  identifier: 9783540374114
  identifier: http://dx.doi.org/10.1007/11817963
  record info:
    record creation date: 101221
    record change date: 20151204150036.0
    record identifier: 978-3-540-37411-4