rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
    sub title: 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings
  name:
    name part: Vounckx, Johan.
    role:
      role term: editor.
  name:
    name part: Azemard, Nadine.
    role:
      role term: editor.
  name:
    name part: Maurine, Philippe.
    role:
      role term: editor.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: gw
    date issued: 2006
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: XVI, 677 p. online resource.
  abstract: Welcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.
  table of contents: Session 1 – High-Level Design -- Session 2 – Power Estimation / Modeling -- Session 3 – Memory and Register Files -- Session 4 – Low-Power Digital Circuits -- Session 5 – Busses and Interconnects -- Session 6 – Low Power Techniques -- Session 7 – Applications and SoC Design -- Session 8 – Modeling -- Session 9 – Digital Circuits -- Session 10 – Reconfigurable and Programmable Devices -- Poster 1 -- Poster 2 -- Poster 3 -- Keynotes -- Industrial Session.
  note: edited by Johan Vounckx, Nadine Azemard, Philippe Maurine.
  subject:
    topic: Computer science
  subject:
    topic: Arithmetic and logic units, Computer
  subject:
    topic: Computer memory systems
  subject:
    topic: Logic design
  subject:
    topic: Microprocessors
  subject:
    topic: Computer system failures
  subject:
    topic: Computers
  subject:
    topic: Computer Science
  subject:
    topic: Theory of Computation
  subject:
    topic: Logic Design
  subject:
    topic: Processor Architectures
  subject:
    topic: System Performance and Evaluation
  subject:
    topic: Arithmetic and Logic Structures
  subject:
    topic: Memory Structures
  classification: QA75.5-76.95
  classification: 004.0151
  related item:
    title info:
      title: Springer eBooks
  related item:
    title info:
      title: Lecture Notes in Computer Science, 4148
  identifier: 9783540390978
  identifier: http://dx.doi.org/10.1007/11847083
  record info:
    record creation date: 100301
    record change date: 20151204184721.0
    record identifier: 978-3-540-39097-8