rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Formal Methods in Computer-Aided Design
    sub title: Second International Conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998, Proceedings
  name:
    name part: Gopalakrishnan, Ganesh.
    role:
      role term: editor.
    role:
      role term: edt
    role:
      role term: http://id.loc.gov/vocabulary/relators/edt
  name:
    name part: Windley, Phillip.
    role:
      role term: editor.
    role:
      role term: edt
    role:
      role term: http://id.loc.gov/vocabulary/relators/edt
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  origin info:
    place:
      place term: gw
    date issued: 1998
    edition: 1st ed. 1998.
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: electronic resource
    reformatting quality: access
    form: remote
    extent: X, 538 p. online resource.
  table of contents: Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck's Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Control with Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS…
  note: edited by Ganesh Gopalakrishnan, Phillip Windley.
  subject:
    topic: Computer-aided engineering
  subject:
    topic: Computer hardware
  subject:
    topic: Computer logic
  subject:
    topic: Mathematical logic
  subject:
    topic: Computational complexity
  subject:
    topic: Computer-Aided Engineering (CAD, CAE) and Design
  subject:
    topic: Computer Hardware
  subject:
    topic: Logics and Meanings of Programs
  subject:
    topic: Mathematical Logic and Formal Languages
  subject:
    topic: Complexity
  classification: TA345-345.5
  classification: 620.00420285
  related item:
    title info:
      title: Springer eBooks
  related item:
    title info:
      title: Lecture Notes in Computer Science, 1522
  identifier: 9783540495192
  identifier: https://doi.org/10.1007/3-540-49519-3
  record info:
    record creation date: 121227
    record change date: 20191021222529.0
    record identifier: 978-3-540-49519-2