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LEADER |
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GR-Antirio624 |
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090227s20012005gr 000 0 gre d |
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|a 1401840302
|
040 |
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|
|a GrPaTEI
|b gre
|c GR-PaULI
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040 |
|
|
|a GrPaTEI
|b gre
|c GR-PaULI
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040 |
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|a GrPaTEI
|b gre
|c GR-PaULI
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082 |
|
0 |
|a 621.395
|2 22
|
100 |
0 |
|
|a Dueck, Robert K.
|
245 |
1 |
0 |
|a Digital design with CPLD applications and VHDL /
|c Dueck, Robert K.
|
250 |
|
|
|a 2nd ed.
|
260 |
|
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|a Clifton Park , N. Y. :
|b Thomson / Delmar Learning,
|c c 2005
|
300 |
|
|
|a xx. , 1004 σ. :
|b εικ. ( some col. ) ;
|c 29 εκ. +
|e 1 cd - rom
|
500 |
|
|
|a Περιλαμβάνει ευρετήριο.
|
650 |
|
0 |
|a Logic design
|
650 |
|
0 |
|a PROGRAMMABLE ARRAY LOGIC
|
650 |
|
0 |
|a VHDL (Computer hardware description language)
|
653 |
|
|
|a PROGRAMMABLE LOGIC DEVICES--DESIGN AND CONSTRUCTION
|
942 |
|
|
|2 ddc
|
952 |
|
|
|0 0
|1 0
|2 ddc
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|6 621_395000000000000_DUE
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|9 261825
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|c BSC
|d 2021-01-17
|e 24
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|r 2021-01-17 00:00:00
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|w 2021-01-17
|y BK15
|x 20090227 0 1
|x GrPaTEI - Antirrio
|
952 |
|
|
|0 0
|1 0
|2 ddc
|4 0
|6 621_395000000000000_DUE
|7 0
|9 261826
|a LISK-2
|b LISK-2
|c BSC
|d 2021-01-17
|e 24
|f 0
|g 0.00
|l 0
|o 621.395 DUE
|p 2430000006763
|r 2021-01-17 00:00:00
|t 1
|w 2021-01-17
|y BK15
|x 20090227 0 1
|x GrPaTEI - Antirrio
|
971 |
|
|
|a .b25704230
|b 01-10-20
|c 12-09-16
|
999 |
|
|
|c 151076
|d 151076
|