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10070988 |
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upatras |
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20210117201633.0 |
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090513s2005 eng |
| 020 |
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|a 9781402031748
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| 040 |
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|a GR-PaULI
|c GR-PaULI
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| 041 |
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|a eng
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| 100 |
1 |
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|a Vanassche, Piet
|9 67832
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| 245 |
1 |
0 |
|a Systematic Modeling and Analysis of Telecom Frontends and Their Building Blocks
|h [electronic resource]
|c by Piet Vanassche, Georges Gielen, Willy Sansen
|
| 260 |
|
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|a Boston, MA
|b Springer
|c 2005
|
| 300 |
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|b v.: digital
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| 490 |
0 |
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|a The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing
|v 842
|x 0893-3405
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| 650 |
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4 |
|a Engineering
|9 17712
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| 650 |
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4 |
|a Computer engineering
|9 24296
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| 650 |
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4 |
|a Electronics
|9 15695
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| 650 |
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4 |
|a Engineering design
|9 64845
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| 650 |
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4 |
|a Engineering
|9 17712
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| 650 |
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4 |
|a Electronic and Computer Engineering
|9 64855
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| 650 |
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4 |
|a Electronics and Microelectronics, Instrumentation
|9 64430
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| 650 |
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4 |
|a Engineering Design
|9 64846
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| 700 |
1 |
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|a Gielen, Georges
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| 700 |
1 |
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|a Sansen, Willy
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| 760 |
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|a The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing
|g 842
|x 0893-3405
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| 852 |
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|a GR-PaULI
|b ΠΑΤΡΑ
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|u http://dx.doi.org/10.1007/1-4020-3174-2
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