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| LEADER |
01366nom a2200373 u 4500 |
| 001 |
10072961 |
| 003 |
upatras |
| 005 |
20210117201739.0 |
| 008 |
090513s2006 eng |
| 020 |
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|a 9780387255569
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| 040 |
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|a GR-PaULI
|c GR-PaULI
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| 041 |
0 |
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|a eng
|
| 100 |
1 |
|
|a Bergeron, Janick
|9 71613
|
| 245 |
1 |
0 |
|a Verification Methodology Manual for SystemVerilog
|h [electronic resource]
|c by Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale
|
| 260 |
|
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|a Boston, MA
|b Synopsys, Inc. and ARM Limited
|c 2006
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| 300 |
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|b v.: digital
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| 650 |
|
4 |
|a Engineering
|9 17712
|
| 650 |
|
4 |
|a Computer engineering
|9 24296
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| 650 |
|
4 |
|a Electronics
|9 15695
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| 650 |
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4 |
|a Computer aided design
|9 24299
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| 650 |
|
4 |
|a Systems engineering
|9 64844
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| 650 |
|
4 |
|a Engineering
|9 17712
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| 650 |
|
4 |
|a Electronic and Computer Engineering
|9 64855
|
| 650 |
|
4 |
|a Electronics and Microelectronics, Instrumentation
|9 64430
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| 650 |
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4 |
|a Computer-Aided Engineering (CAD, CAE) and Design
|9 64865
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| 650 |
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4 |
|a Circuits and Systems
|9 24301
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| 700 |
1 |
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|a Cerny, Eduard
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| 700 |
1 |
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|a Hunter, Alan
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| 700 |
1 |
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|a Nightingale, Andrew
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| 852 |
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|a GR-PaULI
|b ΠΑΤΡΑ
|b ΒΚΠ
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|u http://dx.doi.org/10.1007/b135575
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|d 2016-04-24
|l 0
|r 2016-04-24 00:00:00
|w 2016-04-24
|y ERS
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| 999 |
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|c 49206
|d 49206
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