Writing Testbenches using System Verilog

Writing Testbenches using System Verilog

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας:	Bergeron, Janick
Μορφή:	Ηλεκτρονική πηγή Εργαλειοθήκη Βιβλίο
Γλώσσα:	English
Έκδοση:	Boston, MA Springer Science+Business Media, Inc. 2006
Θέματα:	Engineering Computer engineering System safety Computer aided design Systems engineering Electronic and Computer Engineering Quality Control, Reliability, Safety and Risk Computer-Aided Engineering (CAD, CAE) and Design Circuits and Systems
Διαθέσιμο Online:	http://dx.doi.org/10.1007/0-387-31275-7

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