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LEADER |
01358nom a2200385 u 4500 |
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10073202 |
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upatras |
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20210117201748.0 |
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090513s2006 eng |
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|a 9781402047589
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040 |
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|a GR-PaULI
|c GR-PaULI
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041 |
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|a eng
|
100 |
1 |
|
|a DasGupta, Pallab
|9 72052
|
245 |
1 |
0 |
|a A Roadmap for Formal Property Verification
|h [electronic resource]
|c by Pallab DasGupta
|
260 |
|
|
|a Dordrecht
|b Springer
|c 2006
|
300 |
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|b v.: digital
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650 |
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|a Engineering
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650 |
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4 |
|a Computer engineering
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650 |
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4 |
|a Electronics
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650 |
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4 |
|a Logic design
|9 64563
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650 |
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4 |
|a Computer science
|9 13995
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650 |
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4 |
|a Computer aided design
|9 24299
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650 |
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4 |
|a Systems engineering
|9 64844
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650 |
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|a Engineering
|9 17712
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650 |
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4 |
|a Electronic and Computer Engineering
|9 64855
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650 |
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|a Electronics and Microelectronics, Instrumentation
|9 64430
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650 |
|
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|a Logic Design
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650 |
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|a Mathematical Logic and Formal Languages
|9 67086
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650 |
|
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|a Computer-Aided Engineering (CAD, CAE) and Design
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650 |
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|a Circuits and Systems
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|a GR-PaULI
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|u http://dx.doi.org/10.1007/978-1-4020-4758-9
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|d 2016-04-24
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|w 2016-04-24
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