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LEADER |
01277nom a2200349 u 4500 |
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10091208 |
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20210117202843.0 |
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110802s2010 eng |
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|a 9781441909503
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040 |
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|a GR-PaULI
|c GR-PaULI
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041 |
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|a eng
|
100 |
1 |
|
|a Jayakumar, Nikhil
|9 95489
|
245 |
1 |
0 |
|a Minimizing and Exploiting Leakage in VLSI Design
|h [electronic resource]
|c by Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
|
260 |
|
|
|a Boston, MA
|b Springer Science+Business Media, LLC
|c 2010
|
300 |
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|b v.: digital
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650 |
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4 |
|a Engineering
|9 17712
|
650 |
|
4 |
|a Computer aided design
|9 24299
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650 |
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4 |
|a Systems engineering
|9 64844
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650 |
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4 |
|a Engineering
|9 17712
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650 |
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4 |
|a Circuits and Systems
|9 24301
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650 |
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4 |
|a Computer-Aided Engineering (CAD, CAE) and Design
|9 64865
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700 |
1 |
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|a Paul, Suganth
|9 95490
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700 |
1 |
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|a Garg, Rajesh
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700 |
1 |
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|a Gulati, Kanupriya
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700 |
1 |
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|a Khatri, Sunil P
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710 |
2 |
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|a SpringerLink (Online service)
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852 |
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|a GR-PaULI
|b ΠΑΤΡΑ
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856 |
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|u http://dx.doi.org/10.1007/978-1-4419-0950-3
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