Architectural support for programming languages and operating systems (1991) Proceedings ASPLOS - IV. 4th International Conference Santa Clara, California April 8-11 1991. ACM SIGARCH :vol. 19, no 2, April 1991, ACM SIGOPS : vol. 25, special issue, April 1991, ACM SIGPLAN : vol. 26, no 4, April 1991

• Μορφή: Βιβλίο
• Γλώσσα: Greek
• Έκδοση: New York Association for Computing Machinery 1991
• Θέματα: ACM; Αρχιτεκτονική ηλεκτρονικών υπολογιστών > Συνέδρια; IEEE; OPERATING SYSTEMS; SIGARCH; SIGPLAN; Ηλεκτρονικοί υπολογιστές > Λειτουργικά συστήματα; PROCEEDINGS; ΠΡΑΚΤΙΚΑ ΣΥΝΕΔΡΙΩΝ; ΓΑΛΛΟΠΟΥΛΟΣ

 From the General Chairman   From the Program Chairman   Committees and Referees   Session I : Multiple Instructions Per Cycle Machines   A Variable Instruction Stream Extension to the VLIW Architecture   Reducing the Branch Penalty by Rearranging Instructions in a Double - Width Memory   The Floating Point Performance of a superscalar SPARC Processor   Session II : Cache Conscious Designs   Software Prefetching   High - Bandwidth Data Memory Systems for Superscalar Processors   The Cache Performance and Optimizations of Blocked Algorithms   The Effect of Context Switches on Cache Performance   Session III : Architectural Support for Operating Systems   A Portable Interface for on - the - Fly Instruction Space Modification   Virtual memory Primitives for User Programs   The Interaction of Architecture and Operating System Design   Session IV : Architectural Support for Programming Languages   Integrated Register Allocation and Instruction Scheduling for RISCs   Code Generation for Streaming : an Access / Execute Mechanism   Efficient Implementation of High Lenel Parallel Programs   Session V : Instruction - Level Parallelism   Vector Register Design for Polycyclic Vector Scheduling   Fine - grain Parallelism with Minimal Hardware Support: A Compiler - Controlled Threaded Abstract Machine   Limits of Instruction - Level Parallelism   Session VI : I / O and Operating Systems   Performance Consequences of Parity Placement in Disk Arrays   Integration of Compressiopn and Caching for a Two - Level Filesystem   NUMA Policies and Their Relation to Memory Architecture   Session VII : Architectural Support for Multiprocessors   LimitLESS Directories : A Scalable Cache Coherence Scheme   An Efficient Cache - based Access Anomaly Detection Scheme   Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors   Session VIII : Multiprocessors and Memory Management   Process Coordination with Fetch - and - Increment   Synchronization without Contention   The Case for a Read Barrier   Session IX : Quantitative Analysis of RISCs   An Analysis of SPARC and MIPS InstructionSet Utilization on the SPEC Benchmarks   Performance Characteristics of Architectural Features of the IBM RISC System / 6000   Performance from Architecture : Comparing a RISC and CISC with Similar Hardware Organization   Author Index