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|a 0 89791 101 6
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|a Βιβλιοθήκη ΕΑΙΤΥ
|c Βιβλιοθήκη ΕΑΙΤΥ
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|a XX-XxUND
|c Βιβλιοθήκη ΕΑΙΤΥ
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|a 004.22
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|a Computer Architecture
|b Conference Proceedings of the 10th Annual International Symposium June 13-17, 1983. ACM SIGARCH NEWSLETTER: Vol. 11, No. 3, 1983
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260 |
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|a New York
|b IEEE Computer Society Press
|c 1983
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300 |
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|a ix, 438 p., fig.
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504 |
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|a Includes bibliography, Author Index pp. 437-438
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505 |
1 |
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|a Session 1 : Introduction and Keynote Speech
|a Size, Power, and Speed
|a Session 2 : Computer Architecture Taxonomy
|a Towards a Taxonomy of Computer Architecture Based on thw Machine Data Type View
|a Framework for a Taxonomy of Fault - Tolerance Attributes in Computer Systems
|a Session 3 : Architecture Design Methods
|a Caddie - An Interactive Design Environment
|a On the Verification of Computer Architecture Using an Architecture Description Language
|a Research on Synthesis of Concurrent Computing Systems
|a Session 4 : VLSI Architectures
|a Architecture of the PSC : A programmable Systolic Chip
|a Synchronizing Large VLSI Processor Arrays
|a The Boolean Vector Machine
|a A VLSI Area Machine for Relational Data Bases
|a Session 5A : Data Flow Architecture I
|a Implementing Streams on a Data Flow Computer System with Paged Memory
|a The Piecewise Data Flow Architecture Control Flow and Register Management
|a On the Working Set Concept for Data - Flow Machines
|a A Data Driven System Based on a Microprogrammed Processor Module
|a Session 5B : Cache Memories
|a Architecture of a VLSI Instruction Cache for a RISC
|a Performance of Shared Cache for Parallel - Pipelined Computer Systems
|a Using Cache Memory to Reduce Processor - Memory Traffic
|a A Study of Instruction Cache Organizations and Replacement Policies
|a Section 6A : Multiple Functional Unit Processors
|a Very Long Instruction Word Architectures and the ELI -512
|a A User - Microprogrammable, Local Host Computer with Low-Level Parallelismk
|a Session 6B : Reliability
|a Combining Tags with Error Codes
|a Fault Diagnosis of Bit - Splice Processor
|a Section 7A : Interconnection Networka I
|a Line Digraph Interations and the (d, k) Problem for Directed Graphs
|a Resourcw Allocation in Rectangular CC-Banyans
|a Uniform Theory of the Shuffle-Exchange Type Permutation Networks
|a Section 7B : Performance Evaluation of Scientific Computers
|a Analysis of Gray - 1S Architecture
|a Performance Measurements on HEP - A Pipelined MIMD Computer
|a (SM)2 : Sparse matrix Solving Machine
|a Session 8: Educational Aspects of Computer Architecture
|a An Experimental System for Computer Science Instruction
|a Session 9A : Data Flow Architectures II
|a Execution Control and Memory Science Instruction
|a DDDP : A DIstibuted Data Driven Processor
|a A Data Flow Processor Array System : Design and Anlysis
|a Session 9B : processor and I/O Architectures
|a A Restospective on the Dorado, A High - Performance Personal Computer
|a System / 370 Extended Architecture : A Program View of the Channel Subsystem
|a Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets
|a Session 10A : Interconnection Networks II
|a Switching Strategies in a Class of Packet Switching Networks
|a A Comparative Study of Distributed Resource Sharing on Multiprocessors
|a Concurrent Error Detection in VLSI Interconnection Networks
|a Session 10B : Multicomputers and Multiprocessors
|a Hierarchical Function Distribution - A Design Principle for Advanced Multicomputer Architectures
|a EMMA : An Industrial Experience on Large Multiprocessing Architectures
|a A Communication Structure for a Multiprocessor Computer with Distributed Global Memory
|a Session 11A : Architectural Support for High Level Languages
|a ALPHA : A High - Performance LISP Machine Equipped with a New Stack Structure and Carbage Collection System
|a A Parallel Execution Model of Logic Programs
|a A System Architecture for the Concurrent Evaluation of Applicative Program Expressions
|a A Performance Evaluation of a Lisp - Based Data -Driven Machine (EM3)
|a Session 11B : Architectures for Image Processing
|a A Pyramidal Approach to Parallel Processing
|a The Design of a Parallel Processor for Image Processing On-Board Satellites: An Application Oriented Approach
|a LINKS-1 : A Parallel Pipelined Multimicrocomputer System for Image Creation
|a LIPP - A SIMD Multiprocessor Architecture for Image Processing
|a Special Day : Applied Artificial Intelligence and Its Influence on Computer Architecture
|a The New Generation of Computer Architecture
|a Inference Machine
|a Overview to the Fifth Generation Computer System Project
|a A Relational Data Base Machine : First Step to Knowledge Base Machine
|a A Critique of Multiprocessing von Neumann Style
|a Author Index
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650 |
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4 |
|a ACM
|9 24250
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650 |
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|a COMPUTER ARCHITECTURE
|9 24451
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|a IEEE
|9 24256
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650 |
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4 |
|a SIGARCH
|9 24452
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650 |
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4 |
|a PROCEEDINGS
|9 24278
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650 |
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4 |
|a ΠΡΑΚΤΙΚΑ ΣΥΝΕΔΡΙΩΝ
|9 113060
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650 |
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4 |
|a ΓΑΛΛΟΠΟΥΛΟΣ
|9 113813
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710 |
2 |
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|a IEEE Computer Society
|4 fnd
|9 23536
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710 |
2 |
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|a Association for Computing Machinery
|4 fnd
|9 24263
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852 |
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|a GR-PaULI
|b ΠΑΤΡΑ
|b ΤΜΗΥΠ
|h 004.22
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