Computer Architecture Proceedings of the 18th Annual International Symposium May 27-30, 1991 Toronto, Canada

• Μορφή: Βιβλίο
• Γλώσσα: Greek
• Έκδοση: New York Association for Computing Machinery 1991
• Θέματα: PROCEEDINGS; ACM; SIGARCH; IEEE; COMPUTER ARCHITECTURE; ΠΡΑΚΤΙΚΑ ΣΥΝΕΔΡΙΩΝ; ΓΑΛΛΟΠΟΥΛΟΣ

 General Chair's Message   Program Chair's Message   Organizing Committee   ISCA91 List of Referees   Session 1A : Application - Specific Processors   The SNAP - 1 Parallel AI Prototype   GT - EP : A Novel High - Performance Real - TIme Architecture   IXM2 : A Parallel Associative Processor   Session 1B : Data Prefetching and Branch Prediction   Branch History Table Prediction of Moving Target Branches Due to Subroutine Returns   An Architecture for Software - Controlled Data Prefetching   Data Prefetching in Multiprocessor Vector Cache Memories   Session 2A : Memeory Architecture   Reducing Memory Contention in Shared Memory Multiprocessors   Pseudo-Randomly Interleaved Memory   Evaluation of Memory System Extensions   Session 2B : Interconnection Networks   High Perfarmance Interprocessor Communication Through Optical Wavelength Division Multiple Access Channels   Race - free Interconnection Networks and Multiprocessor Consistency   Deadlock - Free Multicast Wormhole Routing in Multicomputer Networks   Session 3 : Panel   Session 4A : Caching   Dynamic Base Register Caching : A Technique for Reducing Address Bus Width   Implementing a Cache for a High - Performance GaAs Microprocessor   Session 4B : Processor Architecture   Classification and Performance Evaluation of Instruction Buffering Techniques   OHMEGA : A VLSI Superscalar Processor Architecture for Numerical applications   Session 5A : Performance Evaluation of Real Machines   An Empirical Study of the CRAY Y-MP Processor using the PERFECT Club Benchmarks   Instruction Level Profiling and Evaluation of the IBM RS / 6000   Performance Prediction and Tuning on a Multiprocessor   Session 5B : Multicomputer Communications   Performance Evaluation of a Communication System for Transputer - Networks Based on Monitored Event Traces   Chaos router : architecture and performance   Scheduling Pipelined Communication in Distributed Memory Multiprocessors for Real - Time Applications   Session 6A : Shared - Memory Multiprocessors   Detecting Data Races on Weak Memory Systems   On the Validity of Trace - Driven Simulation for Multiprocessors   Comparative Evaluation of Latency Reducing and Tolerating Technigues   Session 6B : Instruction - Level Parallelism   IMPACT : An Architectural Framework for Multiple - Instruction - Issue Processors   Single Instruction Stream Parallelism Is Greater than Two   Exploiting Fine - Grained Parallelism Through a Combination of Hardware and Software Techniques   Session 7 : Panel   Session 8A : Cache Coherence   Comparison of Hardware and Software Cache Coherence Schemes   Modeling the Performance of Limited Pointers Directories for Cache Coherence   Session 8B : Register Sets   Flexible Register Management for Sequential Programs   The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Stratergy   Session 9A : Multithreading and Pipelining   Multithreading : A Revisionist View of Dataflow Architectures   Multi - Threaded Vectorization   Strategies for Achieving Improved processor Throughput   Session 9B : Miscellany   Adaptive Storage Management for Very Large Virtual / Real Storage Systems   Virtualizing the VAX Architecture   Modeling and Measurement of the Impact of Input/Output on System Performane