Computer - Aided Designs Tools for Digital Systems TUTORIAL. A tutorial on design automation tools at the architecture and register - transfer level

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: VANCLEEMPUT, W.M (Συγγραφέας)
Μορφή: Βιβλίο
Γλώσσα:Greek
Έκδοση: New York The Institute of Electrical and Electronic Engineers, Inc. c1979
Έκδοση:2nd ed.
Θέματα:
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040 |a Βιβλιοθήκη ΕΑΙΤΥ  |c Βιβλιοθήκη ΕΑΙΤΥ 
040 |a XX-XxUND  |c Βιβλιοθήκη ΕΑΙΤΥ 
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245 1 0 |a Computer - Aided Designs Tools for Digital Systems  |b TUTORIAL. A tutorial on design automation tools at the architecture and register - transfer level  |c W. M. vanCleemput 
250 |a 2nd ed. 
260 |a New York  |b The Institute of Electrical and Electronic Engineers, Inc.  |c c1979 
300 |a v, 168 p., fig. 
504 |a Περιέχει Βιβλιογραφικές Αναφορές 
505 1 |a Preface  |a Part 1: Introduction  |a The Role of Design Automation in the Design of Digital Systems  |a A Structured Design Automation Environment for Digital Systems  |a Part II : Design Languages  |a A Survey of Computer Hardware Description Language in the USA  |a Introducing PMS  |a An Hierarchical Language for the Structural Description of Digital Systems  |a SCALD:Structured Computer-Aided Logic Design  |a An Architectural Research Facility - ISP Descriptions, Simulation, Data Collection  |a Introducing CDL/ Yaohan Chu  |a Introducing CDL /D.L. Dietmeyer  |a Introducing AHPL / Frederick J. Hill  |a Part III : System Level Description  |a LOGOS and the Software Engineer  |a Modeling for Syntesis - The Gap Between Intent and Behavior  |a State of the Implementation of SARA  |a Multi-Level Modeling in SARA  |a The Graph Model of Behavior Simulator  |a Developing a SARA Building Block - The 8080  |a Specialization of SARA for Software Synthesis  |a Part IV : System Level Simulation  |a Computer System Simulation : An Introduction  |a Part V : Register Transfer and Gate Level Simulation  |a Design Verification at the Register Transfer Language Level  |a Digital Logic Simulation In a Time - Based, Table - Driven Environment. Part 1. Design Verification  |a Digital Logic Simulation In a Time-Based, Table-Driven Environment. Part 2. Parallel Fault Simulation 
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650 4 |a COMPUTER AIDED DESIGN  |9 24299 
650 4 |a DIGITAL SYSTEMS  |9 113234 
650 4 |a ΓΑΛΛΟΠΟΥΛΟΣ  |9 113813 
700 1 |a VANCLEEMPUT, W.M.  |4 aut  |9 127374 
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