System Verilog for Design A Guide to Using System Verilog for Hardware Design and Modeling

• Κύριοι συγγραφείς: Sutherland, Stuart (Συγγραφέας), Davidmann, Simon (Συγγραφέας), Flake, Peter (Συγγραφέας)
• Άλλοι συγγραφείς: Moordy, Phil (XXX)
• Μορφή: Βιβλίο
• Έκδοση: Norwell, Massachusetts Kluwer Academic c2004
• Θέματα: Παραγγελία

 Table of Contents : Forewosd, Preface, Chapter 1. Introduction to System Verilog, Chapter 2. System Verilog Literal Values and Built-in Data Types, Chapter 3. System Verilog User-Defined and Enumerated Data Types, Chapter 4. System Verilog Arrays, Structures and Unions, Chapter 5. System Verilog Procedural Blocks, Tasks and Functions, Chapter 6. System Verilog Procedural Statements, Chapter 7. Modeling Finite State Machines with System Verilog, Chapter 8. System Verilog Design Hierarchy, Chapter 9. System Verilog Interfaces, Chapter 10. A Complete Design Modeled with System Verilog, Chapter 11. Behavioral and Transaction Level Modeling, Appendix A : The System Verilog Formal Definition (BNF), Appendix B : A History of SUPERLOG, The Beginning of System Verilog, Index