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upatras |
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20210914113227.0 |
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040624s |
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|a 1558605576
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| 082 |
0 |
4 |
|a 621.381 52 SUT
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1 |
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|a Logical Effort
|b Designing Fast CMOS Circuits
|c Ivan Sutherland, Bob Sproull, David Harris
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| 260 |
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|a San Francisco
|b Morgan Kaufmann Publishers
|c c1999
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| 300 |
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|a viii,239p.
|b fig.,tabl.
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| 504 |
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|a βιβλιογραφία : σ. 233, ευρετήριο : σσ. 235 - 239, περιέχει ασκήσεις ανα κεφάλαιο.
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| 505 |
1 |
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|a Contents : How it all Started, Preface, 1. The Method of Logical Effort, 2. Design Examples, 3. Deriving the Method of Logical Effort, 4. Calculating the Logical Effort of Gates, 5. Calibrating the Model, 6. Asymmetric Logic Gates, 7. Unegual Rising and Falling Delays, 8. Circuits Families, 9. Forks of Amplifiers, 10. Branches and Interconnect, 11. Wide Structures, 12. Conclusions, Appendices : A. Cast of Characters, B. Reference Process Parameters, C. Solutions to Selected Exercises, Bibliography, Index
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| 650 |
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4 |
|a Λογικός σχεδιασμός
|9 128003
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| 650 |
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4 |
|a CMOS
|9 113287
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| 650 |
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4 |
|a CMOS CIRCUITS
|9 127742
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| 650 |
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4 |
|a DELAY FAULTS (SEMICONDUCTORS)
|9 127743
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| 700 |
1 |
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|a SUTHERLAND, IVAN
|4 aut
|9 127744
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| 700 |
1 |
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|a SPROULL, Bob
|4 aut
|9 127745
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| 700 |
1 |
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|a Harris, David Money
|4 aut
|9 127746
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| 852 |
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|a GR-PaULI
|b ΠΑΤΡΑ
|b ΤΜΗΥΠ
|h 621.381 52
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