Logical Effort Designing Fast CMOS Circuits

• Main Authors: SUTHERLAND, IVAN (Author), SPROULL, Bob (Author), Harris, David Money (Author)
• Format: Book
• Published: San Francisco Morgan Kaufmann Publishers c1999
• Subjects: Λογικός σχεδιασμός; CMOS; CMOS CIRCUITS; DELAY FAULTS (SEMICONDUCTORS)

Table of Contents:

• Contents : How it all Started, Preface, 1. The Method of Logical Effort, 2. Design Examples, 3. Deriving the Method of Logical Effort, 4. Calculating the Logical Effort of Gates, 5. Calibrating the Model, 6. Asymmetric Logic Gates, 7. Unegual Rising and Falling Delays, 8. Circuits Families, 9. Forks of Amplifiers, 10. Branches and Interconnect, 11. Wide Structures, 12. Conclusions, Appendices : A. Cast of Characters, B. Reference Process Parameters, C. Solutions to Selected Exercises, Bibliography, Index