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| LEADER |
01371nam a2200277 u 4500 |
| 001 |
10107505 |
| 003 |
upatras |
| 005 |
20210727143145.0 |
| 008 |
111214s gre |
| 952 |
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|
|0 0
|1 0
|2 ddc
|4 0
|6 005_133000000000000_VAH
|7 0
|8 NFIC
|9 144425
|a LISP
|b LISP
|c ALFe
|d 2016-04-24
|l 0
|o 005.133 VAH
|p 025000284681
|r 2016-04-24 00:00:00
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|x Μεταφορά από Τμ. Μηχανικών ΗΥ & Πληροφορικής
|
| 999 |
|
|
|c 93993
|d 93993
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| 020 |
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|a 9780470052
|
| 040 |
|
|
|a CEID
|c CEID
|
| 040 |
|
|
|a XX-XxUND
|c ΤΜΗΥΠ
|
| 245 |
1 |
0 |
|a VERILOG FOR DIGITAL DESIGN
|c FRANK VAHID, ROMAN LYSECKY
|
| 260 |
|
|
|a UNITED STATES OF AMERICA
|b JOHN WILEY & SONS, INC.
|c 2007
|
| 300 |
|
|
|a vii-xvi, p. 173, fig.
|
| 504 |
|
|
|a index p.p. 163-173
|
| 505 |
1 |
|
|a CHAPTER 2 COMBINATIONAL LOGIC DESIGN P. 9
|a CHAPTER 1 INTRODUCTION P. 1
|a CHAPTER 3 SEQUENTIAL LOGIC DESIGN P. 35
|a CHAPTER 4 DATAPATH COMPONENTS P. 65
|a CHAPTER 5 REGISTER-TRANSFER LEVEL (RTL) DESIGN P. 97
|a CHAPTER 6 VERILOG MINI-REFERENCE P. 129
|
| 650 |
|
4 |
|a Παραγγελία
|9 123966
|
| 650 |
|
4 |
|a DIGITAL DESIGN
|9 129022
|
| 650 |
|
4 |
|a Ηλεκτρονικοί υπολογιστές
|9 263
|x Γλώσσες προγραμματισμού.
|
| 700 |
1 |
|
|a Vahid, Frank
|4 aut
|9 129023
|
| 700 |
1 |
|
|a LYSECKY, ROMAN
|9 129024
|
| 852 |
|
|
|a GR-PaULI
|b ΠΑΤΡΑ
|b ΤΜΗΥΠ
|h 005.133 VAH
|t 1
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| 942 |
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|
|2 ddc
|c BK
|
