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| LEADER |
01367nam a2200301 u 4500 |
| 001 |
10107872 |
| 003 |
upatras |
| 005 |
20210505160547.0 |
| 008 |
120525s gre |
| 020 |
|
|
|a 9780073380
|
| 040 |
|
|
|a CEID
|c CEID
|
| 040 |
|
|
|a XX-XxUND
|c CEID
|
| 245 |
1 |
0 |
|a FUNDAMENTALS OF DIGITAL LOGIC WITH VERILOG DESIGN
|c STEPHEN BROWN; ZVONKO VRANESIC
|
| 250 |
|
|
|b SECOND
|
| 260 |
|
|
|a New York
|b McGraw-Hill Higher Education
|c 2008
|
| 300 |
|
|
|a i-xix,
|b fig.,
|
| 300 |
|
|
|a p. 935
|
| 504 |
|
|
|a p. 935, fig.,
|
| 650 |
|
4 |
|a digital logic
|9 129949
|
| 650 |
|
4 |
|a Παραγγελία
|9 123966
|
| 700 |
1 |
|
|a Brown S., Stephen
|4 aut
|9 129950
|
| 700 |
1 |
|
|a Vranesic, Zvonko G.
|4 aut
|9 127186
|
| 852 |
|
|
|a GR-PaULI
|b ΠΑΤΡΑ
|b ΤΜΗΥΠ
|h 005.133 BRO
|t 1
|
| 852 |
|
|
|a GR-PaULI
|b ΠΑΤΡΑ
|b ΤΜΗΥΠ
|h 005.133 BRO
|t 2
|
| 942 |
|
|
|2 ddc
|
| 952 |
|
|
|0 0
|1 0
|2 ddc
|4 0
|6 005_133000000000000_BRO
|7 0
|8 NFIC
|9 145449
|a LISP
|b LISP
|c ALFe
|d 2016-04-24
|l 0
|o 005.133 BRO
|p 025000282590
|r 2016-04-24 00:00:00
|t 1
|w 2016-04-24
|y BK15
|x Μεταφορά από Τμ. Μηχανικών ΗΥ & Πληροφορικής
|
| 952 |
|
|
|0 0
|1 0
|2 ddc
|4 0
|6 005_133000000000000_BRO
|7 0
|8 NFIC
|9 145450
|a LISP
|b LISP
|c ALFe
|d 2016-04-24
|l 0
|o 005.133 BRO
|p 025000282589
|r 2016-04-24 00:00:00
|t 2
|w 2016-04-24
|y BK15
|x Μεταφορά από Τμ. Μηχανικών ΗΥ & Πληροφορικής
|
| 999 |
|
|
|c 94709
|d 94709
|
