|
|
|
|
LEADER |
03991nam a22004695i 4500 |
001 |
978-0-306-46964-0 |
003 |
DE-He213 |
005 |
20151030101435.0 |
007 |
cr nn 008mamaa |
008 |
100301s2002 xxu| s |||| 0|eng d |
020 |
|
|
|a 9780306469640
|9 978-0-306-46964-0
|
024 |
7 |
|
|a 10.1007/b116777
|2 doi
|
040 |
|
|
|d GrThAP
|
050 |
|
4 |
|a QA76.9.M3
|
072 |
|
7 |
|a UYZM
|2 bicssc
|
072 |
|
7 |
|a UKR
|2 bicssc
|
072 |
|
7 |
|a BUS083000
|2 bisacsh
|
072 |
|
7 |
|a COM032000
|2 bisacsh
|
082 |
0 |
4 |
|a 005.74
|2 23
|
100 |
1 |
|
|a Parhami, Behrooz.
|e author.
|
245 |
1 |
0 |
|a Introduction to Parallel Processing
|h [electronic resource] :
|b Algorithms and Architectures /
|c by Behrooz Parhami.
|
264 |
|
1 |
|a Boston, MA :
|b Springer US,
|c 2002.
|
300 |
|
|
|a XXIII, 532 p.
|b online resource.
|
336 |
|
|
|a text
|b txt
|2 rdacontent
|
337 |
|
|
|a computer
|b c
|2 rdamedia
|
338 |
|
|
|a online resource
|b cr
|2 rdacarrier
|
347 |
|
|
|a text file
|b PDF
|2 rda
|
490 |
1 |
|
|a Series in Computer Science,
|x 1567-7974
|
505 |
0 |
|
|a Fundamental Concepts -- to Parallelism -- A Taste of Parallel Algorithms -- Parallel Algorithm Complexity -- Models of Parallel Processing -- Extreme Models -- PRAM and Basic Algorithms -- More Shared-memory Algorithms -- Sorting and Selection Networks -- Other Circuit-Level Examples -- Mesh-Based Architectures -- Sorting on a 2D Mesh or Torus -- Routing on a 2D Mesh or Torus -- Numerical 2D Mesh Algorithms -- Other Mesh-Related Architectures -- Low-Diameter Architectures -- Hypercubes and Their Algorithms -- Sorting and Routing on Hypercubes -- Other Hypercubic Architectures -- A Sampler of Other Networks -- Some Broad Topics -- Emulation and Scheduling -- Data Storage, Input, and Output -- Reliable Parallel Processing -- System and Software Issues -- Implementation Aspects -- Shared-Memory MIMD Machines -- Message-Passing MIMD Machines -- Data-Parallel SIMD Machines -- Past, Present, and Future.
|
520 |
|
|
|a THE CONTEXT OF PARALLEL PROCESSING The field of digital computer architecture has grown explosively in the past two decades. Through a steady stream of experimental research, tool-building efforts, and theoretical studies, the design of an instruction-set architecture, once considered an art, has been transformed into one of the most quantitative branches of computer technology. At the same time, better understanding of various forms of concurrency, from standard pipelining to massive parallelism, and invention of architectural structures to support a reasonably efficient and user-friendly programming model for such systems, has allowed hardware performance to continue its exponential growth. This trend is expected to continue in the near future. This explosive growth, linked with the expectation that performance will continue its exponential rise with each new generation of hardware and that (in stark contrast to software) computer hardware will function correctly as soon as it comes off the assembly line, has its down side. It has led to unprecedented hardware complexity and almost intolerable dev- opment costs. The challenge facing current and future computer designers is to institute simplicity where we now have complexity; to use fundamental theories being developed in this area to gain performance and ease-of-use benefits from simpler circuits; to understand the interplay between technological capabilities and limitations, on the one hand, and design decisions based on user and application requirements on the other.
|
650 |
|
0 |
|a Computer science.
|
650 |
|
0 |
|a Management information systems.
|
650 |
1 |
4 |
|a Computer Science.
|
650 |
2 |
4 |
|a Management of Computing and Information Systems.
|
710 |
2 |
|
|a SpringerLink (Online service)
|
773 |
0 |
|
|t Springer eBooks
|
776 |
0 |
8 |
|i Printed edition:
|z 9780306459702
|
830 |
|
0 |
|a Series in Computer Science,
|x 1567-7974
|
856 |
4 |
0 |
|u http://dx.doi.org/10.1007/b116777
|z Full Text via HEAL-Link
|
912 |
|
|
|a ZDB-2-SCS
|
912 |
|
|
|a ZDB-2-BAE
|
950 |
|
|
|a Computer Science (Springer-11645)
|