System-on-a-Chip Verification Methodology and Techniques /

• Κύριοι συγγραφείς: Rashinkar, Prakash (Συγγραφέας), Paterson, Peter (Συγγραφέας), Singh, Leena (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Boston, MA : Springer US, 2002.
• Θέματα: Engineering.; Computers.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Computer-Aided Engineering (CAD, CAE) and Design.; Computing Methodologies.; Electrical Engineering.

 System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application. System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter: Explanation of the objective involved in performing verification after a given design step; Features of options available; When to use a particular option; How to select an option; and Limitations of the option. This exciting new book will be of interest to all designers and test professionals. 

 System-level Verification -- Block-level Verification -- Analog/Mixed Signal Simulation -- Simulation -- Hardware/Software Co-verification -- Static Netlist Verification -- Physical Verification and Design Sign-off.