Principles of Verifiable RTL Design A Functional Coding Style Supporting Verification Processes in Verilog /
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improveme...
Κύριοι συγγραφείς: | Bening, Lionel (Συγγραφέας), Foster, Harry (Συγγραφέας) |
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Συγγραφή απο Οργανισμό/Αρχή: | SpringerLink (Online service) |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Boston, MA :
Springer US,
2000.
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Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
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