Principles of Verifiable RTL Design A Functional Coding Style Supporting Verification Processes in Verilog /

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improveme...

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Bibliographic Details
Main Authors: Bening, Lionel (Author), Foster, Harry (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: Boston, MA : Springer US, 2000.
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ΒΚΠ - Πατρα: ALFd

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Call Number: 330.01 BAU
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ΒΚΠ - Πατρα: BSC

Holdings details from ΒΚΠ - Πατρα: BSC
Call Number: 330.01 BAU
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