Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms

Εμφάνιση άλλων εκδόσεων (1)

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς:	Hachtel, Gary D. (Συγγραφέας), Somenzi, Fabio (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή:	SpringerLink (Online service)
Μορφή:	Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:	English
Έκδοση:	Boston, MA : Springer US, 1996.
Θέματα:	Engineering. Computer logic. Computer science > Mathematics. Computers. Computer-aided engineering. Electrical engineering. Electronic circuits. Circuits and Systems. Logics and Meanings of Programs. Electrical Engineering. Computer-Aided Engineering (CAD, CAE) and Design. Discrete Mathematics in Computer Science. Computing Methodologies.
Διαθέσιμο Online:	Full Text via HEAL-Link

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