Logic Synthesis and Verification Algorithms

• Κύριοι συγγραφείς: Hachtel, Gary D. (Συγγραφέας), Somenzi, Fabio (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Boston, MA : Springer US, 1996.
• Θέματα: Engineering.; Computer logic.; Computer science > Mathematics.; Computers.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Logics and Meanings of Programs.; Electrical Engineering.; Computer-Aided Engineering (CAD, CAE) and Design.; Discrete Mathematics in Computer Science.; Computing Methodologies.

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis...

Πίνακας περιεχομένων:

• A Quick Tour of Logic Synthesis with the Help of a Simple Example
• Two Level Logic Synthesis
• Boolean Algebras
• Synthesis of Two-Level Circuits
• Heuristic Minimization of Two-level Circuits
• Binary Decision Diagrams (BDDs)
• Models of Sequential Systems
• Models of Sequential Systems
• Synthesis and Verification of Finite State Machines
• Finite Automata
• Multilevel Logic Synthesis
• Multi-Level Logic Synthesis
• Multi-Level Minimization
• Automatic Test Generation for Combinational Circuits
• Technology Mapping.