Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis...
| Main Authors: | , |
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| Corporate Author: | |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
1996.
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| Subjects: | |
| Online Access: | Full Text via HEAL-Link |
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