The Complete Verilog Book

• Κύριος συγγραφέας: Sagdeo, Vivek (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Boston, MA : Springer US, 1998.
• Θέματα: Engineering.; Computer hardware.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Computer Hardware.; Computer-Aided Engineering (CAD, CAE) and Design.; Electrical Engineering.

 The Verilog hardware description language (HDL) provides the ability to describe digital and analog systems. This ability spans the range from descriptions that express conceptual and architectural design to detailed descriptions of implementations in gates and transistors. Verilog was developed originally at Gateway Design Automation Corporation during the mid-eighties. Tools to verify designs expressed in Verilog were implemented at the same time and marketed. Now Verilog is an open standard of IEEE with the number 1364. Verilog HDL is now used universally for digital designs in ASIC, FPGA, microprocessor, DSP and many other kinds of design-centers and is supported by most of the EDA companies. The research and education that is conducted in many universities is also using Verilog. This book introduces the Verilog hardware description language and describes it in a comprehensive manner. Verilog HDL was originally developed and specified with the intent of use with a simulator. Semantics of the language had not been fully described until now. In this book, each feature of the language is described using semantic introduction, syntax and examples. Chapter 4 leads to the full semantics of the language by providing definitions of terms, and explaining data structures and algorithms. The book is written with the approach that Verilog is not only a simulation or synthesis language, or a formal method of describing design, but a complete language addressing all of these aspects. This book covers many aspects of Verilog HDL that are essential parts of any design process. 

 to Verilog HDL -- Data Types in Verilog -- Abstraction Levels in Verilog: Behavioral, RTL, and Structural -- Semantic Model for Verilog HDL -- Behavioral Modeling -- Structural Primitive Modeling -- Mixed Structural, RTL, and Behavioral Design -- System Tasks and Functions -- Compiler Directives -- Interactive Simulation and Debugging -- System Examples -- Synthesis with Verilog -- Verilog Subset for Logic Synthesis -- Special Considerations in Synthesizing Verilog -- Specify Blocks — Timing Descriptions -- Programming Language Interface -- Strength Modeling with Transistors -- Standard Delay Format -- Verilog-A and Verilog-MS -- Simulation Speedup Techniques -- Formal Syntax Definition for Verilog HDL -- Verilog Subset for Logic Synthesis -- Programming Language Interface (PLI) Header File — veriuser.h -- Programming Language Interface (PLI) header File — acc _user.h -- Programming Language Interface (PLI) Header File — vpi_user.h file -- Formal Syntax Definition of SDF.